Recently, multichannel neural interface systems have been implemented to monitor neural activities. For the comprehensive analysis of neural activities, it is desirable to realize simultaneous real-time monitoring of multiple sites in 3D electrode arrays with 64 channels or more. Typically, neural activities such as spike contain most of their information in the bandwidth below 10 kHz with maximum amplitude of ±500 μV. In these microsystems, the neural signals should be amplified and converted into digital signals to be transmitted to wired/wireless communication channels between the implanted system and the external world. Simultaneous access of multiple sites should be done in a manner that utilizes analog-to-digital converters (ADC) having good noise immunity in a small form factor at low power.
A successive approximation register (SAR) ADC is one of the suitable candidates for neural interface applications due to its simplicity, low power consumption, and reasonable resolution. With a gain of 60 dB prior to the ADC, the quantization noise is required to be less than 5 mVrms which can be achieved by 8 bit or higher resolution capability of ADC. FIG. 1 shows a conventional 8 bit SAR ADC structure which typically consists of three parts: capacitor array (for sample and hold and DAC), comparator, and successive approximation register (SAR). For relatively lower resolution ADCs (<6 b), the comparator and SAR consume most of the power. However, as the resolution of ADCs increases, the power consumption required for charging and discharging the capacitor array becomes significant. Also, the total capacitance required for DAC increases exponentially proportional to the number of bits. In the high resolution ADCs, the capacitor array takes most of the area and power consumption. It becomes more important to reduce the total capacitance and area as the number of bits required in ADC increases and multiple implementations of ADCs is needed. You-Kuang et al. reported an effective switching method to reduce the power. However, this switching technique can reduce only half of the power in conventional capacitor arrays. Yang et al. proposed an energy-efficient ADC with a small form factor. However, a relatively complex algorithm may be needed for practical use in neural microsystems.